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| MM74HC245A Octal 3-STATE Transceiver September 1983 Revised May 2005 MM74HC245A Octal 3-STATE Transceiver General Description The MM74HC245A 3-STATE bidirectional buffer utilizes advanced silicon-gate CMOS technology, and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving large bus capacitances. This circuit possesses the low power consumption and high noise immunity usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits. This device has an active LOW enable input G and a direction control input, DIR. When DIR is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from the B inputs to the A outputs. The MM74HC245A transfers true data from one bus to the other. This device can drive up to 15 LS-TTL Loads, and does not have Schmitt trigger inputs. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 13 ns s Wide power supply range: 2-6V s Low quiescent current: 80 PA maximum (74 HC) s 3-STATE outputs for connection to bus oriented systems s High output drive: 6 mA (minimum) s Same as the 645 Ordering Code: Order Number MM74HC245AWM MM74HC245ASJ MM74HC245AMTC MM74HC245AN Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Truth Table Control Inputs G L L H H HIGH Level L LOW Level X Irrelevant Operation DIR L H X B data to A bus A data to B bus Isolation Top View (c) 2005 Fairchild Semiconductor Corporation DS005165 www.fairchildsemi.com MM74HC245A Logic Diagram www.fairchildsemi.com 2 MM74HC245A Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage DIR and G pins (VIN) DC Input/Output Voltage (VIN , VOUT) Clamp Diode Current (ICD) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise/Fall Times (tr, tf) VCC VCC VCC 2.0V 4.5V 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC 40 85 qC Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: 12 mW/qC from 65qC to 85qC. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN VIH or VIL (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 25qC TA Conditions 40 to 85qC TA 55 to 125qC Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 Units V V V V V V V V V V V V V V V V |IOUT| d 20 PA 2.0V 4.5V 6.0V VIN VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V |IOUT| d 6.0 mA |IOUT| d 7.8 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT| d 20 PA VIN VIH or VIL 4.5V 6.0V 6.0V 6.0V 6.0V |IOUT| d 6.0 mA |IOUT| d 7.8 mA IIN IOZ ICC Input Leakage Current (G and DIR) Maximum 3-STATE Output Leakage Current Maximum Quiescent Supply Current VOUT VIN IOUT VCC or GND VIH VCC or GND 0 PA VIN VCC to GND r0.1 r0.5 8.0 r1.0 r5.0 80 r1.0 r10 160 PA PA PA Enable G Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC245A AC Electrical Characteristics VCC 5V, TA 25qC, tr tf 6ns Parameter Conditions CL RL CL RL CL 45 pF 1 k: 45 pF 1 k: 5 pF 18 25 ns Typ 12 24 Guaranteed Limit 17 35 Units ns ns Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Maximum Propagation Delay Maximum Output Enable Time Maximum Output Disable Time AC Electrical Characteristics VCC 2.0V to 6.0V, CL 50 pF, tr tf 6ns (unless otherwise specified) Conditions CL CL CL CL CL CL 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 71 81 26 31 21 25 39 20 18 20 6 5 50 5 5 15 10 20 10 20 10 20 190 240 38 48 32 41 135 27 23 60 12 10 240 300 48 60 41 51 169 34 29 75 15 13 285 360 57 72 48 61 203 41 34 90 18 15 ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF pF VCC 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V TA Typ 31 41 13 17 11 14 90 96 18 22 15 19 25qC TA Symbol tPHL, tPLH Parameter Maximum Propagation Delay 40 to 85qC TA 55 to 125qC Guaranteed Limits 113 116 23 28 19 23 135 128 27 33 23 28 Units ns ns ns ns ns ns tPZH, tPZL Maximum Output Enable Time RL CL CL CL CL CL CL tPHZ, tPLZ Maximum Output Disable Time RL CL tTLH, tTHL Output Rise and Fall Time CL 50 pF CPD CIN CIN/OUT Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Maximum Input/Output Capacitance, A or B G G VIL VIH Note 5: CPD determines the no load dynamic power consumption, PD CPD VCC2 fICC VCC, and the no load dynamic current consumption, IS CPD VCC fICC. www.fairchildsemi.com 4 MM74HC245A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC245A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC245A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC245A Octal 3-STATE Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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